SH7764 Datasheet, PDF (1477/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Power-Down Mode
28.5 Refresh Standby Mode
28.5.1 Transition to Refresh Standby Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the
program execution state to refresh standby mode. In refresh standby mode, not only the CPU but
also the clock and on-chip peripheral modules halt. However, the clock output from the CLKOUT
pin continues.
The contents of the CPU and cache registers remain unchanged. Some registers of the on-chip
peripheral modules are initialized.
The procedure for a transition to software standby mode is as follows:
1. Set the STBY bit in STBCR to 1.
2. Execute the SLEEP instruction.
3. Software standby mode is entered and the clocks within the LSI are halted. The output on the
STATUS0 pin goes high.
28.5.2 Canceling Refresh Standby Mode
Refresh standby mode is canceled by an interrupt (NMI or IRQ/IRL) or a reset.
(1) Canceling with Interrupt
When an NMI or IRQ, occurs, refresh standby mode is canceled and the STATUS0 pin goes low.
Thereafter, interrupt exception handling is executed and a code indicating the interrupt source is
set in INTEVT. After branching to the interrupt service routine, clear the STBY bit in the STBCR
register back to 0. Since interrupts are accepted in refresh standby mode even when the BL bit in
SR is 1, save SPC and SSR to the stack before executing the SLEEP instruction if necessary.
Immediately after an interrupt is detected, the clock output on the CLKOUT pin may be unstable
until software standby mode is canceled.
(2) Canceling with Reset
Refresh standby mode is cancelled by a power-on reset by the PRESET pin.
Rev. 1.00 Nov. 22, 2007 Page 1421 of 1692
REJ09B0360-0100