SH7764 Datasheet, PDF (629/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
Consequently, when receiving data continuously, be sure to clear the status of MDR and SDR
after reading the receive data register.
(2) MDE and SDE
If the MDE or SDE status bits are still set data in the transmit data register is to be transmitted on
the I²C bus by the slave or master, the SCL line must be held low until the MDE and SDE status
bits are reset. The MDE or SDE status bit being set indicates that the data currently held in the
Transmit Data Register has already been transmitted on the I²C bus.
The software must clear this status bit when it writes to the transmit data register which is ready to
transmit subsequent data bytes. This is not required for the first byte of data to be transmitted on
the bus.
(3) MAL
When the master loses arbitration, the MAL bit (of the master status register) is set and the MIE
bit (of the master control register) is reset. At this point, master mode is invalid and the I²C bus
interface enters the slave mode. When master operation is restarted, data transfer from the master
begins after the MAL bit has been cleared.
(4) SAR
The SAR status bit is set when the slave identifies its address on the I²C bus. At this point the
slave interface forces the SCL line low until the SAR status bit is reset.
This is particularly important when a slave transmit is about to take place on the bus, and the slave
will transmit the data from the transmit data register. The software responds to the SAR status by
writing the required data into the transmit data register and then resetting the SAR status bit. This
allows the slave interface to continue the access.
When the slave is about to receive data, the software may be reading data loaded in a previous
access from the receive data register. In this case the valid data still held in the receive data
register is overwritten. However, this is avoided using the SAR status bit. After the software has
read data in the receive data register, reset the SAR bit (if it is set). Then overwriting the receive
data register is avoided.
Rev. 1.00 Nov. 22, 2007 Page 573 of 1692
REJ09B0360-0100