SH7764 Datasheet, PDF (16/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

13.3.5 Interrupt Mask Register (INTMSK) ..................................................................... 424
13.3.6 Interrupt Mask Clear Register (INTMSKCLR) .................................................... 425
13.3.7 NMI Flag Control Register (NMIFCR) ................................................................ 426
13.3.8 User Interrupt Mask Level Register (USERIMASK) ........................................... 428
13.3.9 On-Chip Module Interrupt Priority Registers (INT2PRI0 to INT2PRI12) ........... 430
13.3.10 Interrupt Source Register 0 (Mask State is not affected) (INT2A0) ..................... 432
13.3.11 Interrupt Source Register 01 (Mask State is not affected) (INT2A01) ................. 434
13.3.12 Interrupt Source Register (Mask State is affected) (INT2A1) .............................. 436
13.3.13 Interrupt Source Register 11 (Mask State is affected) (INT2A11) ....................... 438
13.3.14 Interrupt Mask Register (INT2MSKR)................................................................. 440
13.3.15 Interrupt Mask Register 1 (INT2MSKR1)............................................................ 442
13.3.16 Interrupt Mask Clear Register (INT2MSKCR) .................................................... 444
13.3.17 Interrupt Mask Clear Register 1 (INT2MSKCR1)................................................ 446
13.3.18 On-Chip Module Interrupt Source Registers
(INT2B0 and INT2B2 to INT2B7) ....................................................................... 448
13.3.19 GPIO Interrupt Set Register (INT2GPIC) .............................................................. 453
13.4 Interrupt Sources................................................................................................................ 455
13.4.1 NMI Interrupt........................................................................................................ 455
13.4.2 IRQ Interrupts....................................................................................................... 455
13.4.3 On-Chip Module Interrupts .................................................................................. 456
13.4.4 Interrupt Priority Level of On-Chip Module Interrupts ........................................ 456
13.4.5 Interrupt Exception Handling and Priority............................................................ 457
13.5 Operation ........................................................................................................................... 462
13.5.1 Interrupt Sequence ................................................................................................ 462
13.5.2 Multiple Interrupts ................................................................................................ 464
13.5.3 Interrupt Masking by MAI Bit.............................................................................. 464
13.6 Interrupt Response Time.................................................................................................... 465
13.7 Usage Notes ....................................................................................................................... 466
13.7.1 To Clear Interrupt Request When Holding Function Selected ............................. 466
13.7.2 Notes on Setting IRQ1 and IRQ0 Pin Function .................................................... 467
13.7.3 To Clear IRQ Interrupt Requests .......................................................................... 467
Section 14 Timer Unit (TMU)........................................................................... 469
14.1 Features.............................................................................................................................. 469
14.2 Input/Output Pins............................................................................................................... 471
14.3 Register Descriptions......................................................................................................... 472
14.3.1 Timer Output Control Register (TOCR)............................................................... 474
14.3.2 Timer Start Register (TSTR0, TSTR1)................................................................. 475
14.3.3 Timer Constant Register (TCORn) (n = 0 to 5) .................................................... 477
14.3.4 Timer Counter (TCNTn) (n = 0 to 5).................................................................... 477
Rev. 1.00 Nov. 22, 2007 Page xvi of lvi