SH7764 Datasheet, PDF (328/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Bit
2 to 0
Initial
Bit Name Value R/W
SMS2 to 000 R/W
SMS0
Description
SDRAM Mode Select
These bits initialize the SDRAM at a power-on or after
release of a reset. By setting these bits by software, the
following commands are issued. For details on the
initialization procedure, see section 11.7.9, SDRAM
Initialization Sequence.
Each time this register is written, the command is
issued once.
000: Normal operation
001: The NOP command is issued (valid only when the
DCE bit in MIM is set to 1).
010: The PALL command is issued (valid only when
the DCE bit in MIM is set to 1).
011: The CKE signal is enabled, and at the same time,
the DESELECT command is issued (valid only
when the DCE bit in MIM is set to 1).
100: The CBR (auto) refresh command is issued (valid
only when the DCE bit in MIM is set to 1).
Settings other than above are prohibited. If a prohibited
value is set, correct operation is not guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 272 of 1692
REJ09B0360-0100