SH7764 Datasheet, PDF (388/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.7.7 Bank Open Mode
The SDRAM bank function can be used to support high-speed accesses to the same row address.
Specifically, when the BOMODE[1:0] bits in MIM are 00, read/write accesses are performed,
using the commands without auto-precharge (READ/WRIT). In this case, precharge is not carried
out when an access is completed. Therefore, when the next access is an access to the same row
address in the same bank, the READ or WRIT command can be immediately issued without
issuing the ACTV command. The SDRAM is internally divided into four banks, and a single row
address can be held in the active state for each bank. On the other hand, when the next access is an
access to the different row address, the PRE command is first issued to precharge the relevant
bank. After precharge has been completed, the ACTV command is accessed followed by the
READ or WRIT command. In the applications where the different row addresses are
consecutively accessed, access time increases because precharge is started after an access request
has been issued.
There is a limit on tRAS, i.e., the time duration for which each bank can be held in the active state.
If there is no guarantee that this time limit can be kept by program execution when a cache hit
does not occur and thus another row will be accessed, it is necessary to set auto-refreshing and set
the refresh cycle to no more than the maximum value of tRAS. This allows keeping the limit value
of the active time for each bank. When the auto-refresh function is not used, some measures
should be taken through programming to prevent each bank from being held in the active state
over the specified time.
Figure 11.16 shows the burst read timing for the same row address, and figure 11.17 shows the
burst read timing for the different row addresses. Similarly, figure 11.18 shows the burst write
timing for the same row address, and figure 11.19 shows the burst write timing for the different
row addresses.
Rev. 1.00 Nov. 22, 2007 Page 332 of 1692
REJ09B0360-0100