SH7764 Datasheet, PDF (1082/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
Bit
Bit Name Initial Value R/W Description
12
VEINTEN 0
R/W Vsync Ending Point Interrupt Enable
Enables or disables the generation of an interrupt at
the end point of LCDC's Vsync.
0: Interrupt at the end point of the Vsync signal is
disabled
1: Interrupt at the end point of the Vsync signal is
enabled
11
MINTS
0
R/W Memory Access Interrupt State
Indicates the memory access interrupt handling
state.
This bit indicates 1 when the LCDC memory access
interrupt is generated (set state). During the
memory access interrupt handling routine, this bit
should be cleared by writing 0.
0: LCDC did not generate a memory access
interrupt or has been informed that the generated
memory access interrupt has completed
1: LCDC has generated a memory access end
interrupt and not yet been informed that the
generated memory access interrupt has
completed
10
FINTS
0
R/W Flame End Interrupt State
Indicates the flame end interrupt handling state.
This bit indicates 1 at the time when the LCDC
flame end interrupt is generated (set state). During
the flame end interrupt handling routine, this bit
should be cleared by writing 0.
0: LCDC did not generate a flame end interrupt or
has been informed that the generated flame end
interrupt has completed
1: LCDC has generated a flame end interrupt and
not yet been informed that the generated flame
end interrupt has completed
Rev. 1.00 Nov. 22, 2007 Page 1026 of 1692
REJ09B0360-0100