SH7764 Datasheet, PDF (1295/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.1 Graphics Block Control Registers (GRCMEN1 to GRCMEN4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WE 













Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0













 DEN VEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R/W R/W
Initial
Bit
Bit Name Value
31
WE
0
30 to 2 
All 0
1
DEN
0
0
VEN
0
R/W Description
R/W Enables register value transfer. Writing 1 to this bit
transfers the register values (registers at H'000 to
H'31C and H'32C) in synchronization with Vsync.
After register transfer is competed, this bit is
cleared to 0.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Enables graphics display.
0: Disables display operation
1: Enables display operation
R/W Enables lower-layer graphics display.
0: Disables display operation
1: Enables display operation
Rev. 1.00 Nov. 22, 2007 Page 1239 of 1692
REJ09B0360-0100