SH7764 Datasheet, PDF (1320/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.19 Horizontal Sync Signal Timing Control Register (HSYNCTIM)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16





HSYNC_START[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





HSYNC_END[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 27 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
26 to 16 HSYNC_START H'000 R/W
[10:0]
These bits should always be set to H'000. These
bits specify in number of panel clock cycles the
interval between the internal horizontal sync signal
and the point where the horizontal sync signal
(HSYNC) for the screen is set to 1.
15 to 11 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0
HSYNC_END H'00A R/W
[10:0]
These bits specify in number of panel clock cycles
the interval between the internal horizontal sync
signal and the point where the horizontal sync
signal (HSYNC) for the screen is cleared to 0.
Note: Be sure to satisfy HSYNC_START ≠ HSYNC_END; otherwise, correct operation is not
guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1264 of 1692
REJ09B0360-0100