SH7764 Datasheet, PDF (382/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
SH7764
A[14:0]
CLKOUT
CKE
CS1
RAS
CAS
R/W
D31 to D16
DQMUU
DQMUL
D15 to D0
DQMLU
DQMLL
128-Mbit (16-MB)
SDRAM
8M × 16 bits
BA[1:0], A[11:0]
CLK
CKE
CS
RAS
CAS
WE
I/O15 to I/O0
DQMU
DQML
BA[1:0], A[11:0]
CLK
CKE
CS
RAS
CAS
WE
I/O15 to I/O0
DQMU
DQML
Figure 11.11 Connection Example of Synchronous DRAMs for 32-Bit Data Bus (Area 1)
11.7.2 Address Multiplexing
Address multiplexing is performed so that the SDRAM is connected without the external address
multiplexing circuit according to the setting of the BW[1:0] bits in MIM and the SPLIT[3:0] bits
in SDRA. Table 11.18 shows the relationship between the bits to be multiplexed and the address
bits to be output to the address pins.
Note that the address output to the A25 to A15 pins are not guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 326 of 1692
REJ09B0360-0100