SH7764 Datasheet, PDF (1491/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

WDTCNT value
WDTST
Incremented on each
WDTBCNT overflow
H'0000 0000
WDTBCNT value
H'0003 FFFF
Incremented every
peripheral clock (Pck)
cycle
Cleared to 0
on overflow
Section 29 Watchdog Timer and Reset
Cleared to 0
on overflow
Time
H'0000 0000
TME
WOVF
IOVF
Counting starts
Flag is set
Time
Figure 29.2 WDT Counting Operations (Example in Interval Timer Mode)
WDTBCNT is a 18-bit up-counter operated on the peripheral clock (Pck). WDTBCNT is cleared
when H'55 is set to the bits 31 to 24 in WDTBST.
If the peripheral clock frequency is 50 MHz, the WDTBCNT overflow time is approximately
5.243 ms (= 2^18 [bit] × 1/50 [MHz]).
WDTCNT is a 12-bit counter, starts count up operation when overflow occurs in WDTBCNT. The
time until WDTCNT overflows becomes the maximum value when H'000 are set to WDTST.
Where the peripheral clock frequency is 50 MHz, the maximum overflow time is approximately
21.475 s (= 2^12 [bit] × 5.243 [ms]).
And the time until WDTCNT overflows becomes the minimum value when H'001 is set to
WDTST. The minimum overflow time is approximately 5.243 ms (= 2^1 [bit] × 5.243 [ms]).
29.4.5 Clearing WDT Counter
Writing H'55 to WDTBST with longword access clears WDTBCNT and writing the overflow
setting value to WDTST clears WDTCNT.
Rev. 1.00 Nov. 22, 2007 Page 1435 of 1692
REJ09B0360-0100