SH7764 Datasheet, PDF (523/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.7.2 Notes on Setting IRQ1 and IRQ0 Pin Function
When switching the IRQ1 and IRQ0 pin function, it is possible that the INTC may hold an
interrupt by mistake. Therefore, to prevent detecting unintentional interrupts, mask both all IRQ
interrupts and then switch the IRQ1 and IRQ0 pin function.
Table 13.8 Switching Sequence of IRQ1 and IRQ0 Pin Function
Sequence ITEM
1
IRQ interrupt request masking
2
IRQ0/DTEND1 pin setting to IRQ0
interrupt request input
3
WDTOVF/IRQ1/AUDUCK/DACK1 pin
setting to IRQ1 interrupt request input
4
IRQ interrupt detection start
PROCEDURE
Write 1 to all bits in INTMSK
Write 0 to the PTSEL_SI5 bit in the
PTSEL_S in the GPIO
Write 01 to the PTSEL_K7[1:0] bits in the
PTSEL_K in GPIO
Write 1 to the corresponding bit in
INTMSKCLR
13.7.3 To Clear IRQ Interrupt Requests
Clearing procedure of the interrupt held in the INTC is as follows
• To clear IRQ level-sense interrupt requests
To clear an IRQ level-sense interrupt request from the IRQ1 and IRQ0 pins, write 1 to the
corresponding mask bit (IM01 and IM00) in INTMSK.
The IRQ interrupt requests detected by the INTC is not cleared even if 0 is written to a
corresponding bit in INTPRI. The IRQ interrupt sources detected by the INTC (be cleared)
• To clear IRQ edge-detection interrupt requests
To clear an IRQ edge-detection interrupt request from the IRQ1 and IRQ0 pins, write 0 after
reading 1 in the corresponding IRn (n = 0, 1) bit in INTREQ.
The IRQ interrupt requests detected by the INTC is not cleared even if 1 is written to a
corresponding bit in INTMSK.
Rev. 1.00 Nov. 22, 2007 Page 467 of 1692
REJ09B0360-0100