SH7764 Datasheet, PDF (1298/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Pixel bus
MSB
127
16 bits
15
0
RGB0
RGB1
RGB2
128 bits
RGB3 RGB4
RGB5
RGB6
LSB
127
RGB7
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Note: The image is displayed in the order of pixels (RGB0 -> RGB1 -> RGB2 -> ... -> RGB6 -> RGB7) from left to right.
Figure 24.8 Pixel Bus Endian (ENDIAN = 1)
24.6.3 Graphic Image Base Address Registers (GROPSADR1 to GROPSADR4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



GROPSADR[28:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
GROPSADR[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 29 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
28 to 0
GROPSADR H'0000000 R/W
[28:0]
These bits specify the address from which a
graphic image is to be read. The lowest bit should
always be 0.
Note: The VDC2 processes 16-bit RGB data; it cannot handle data located beyond a 2-byte
alignment boundary.
Rev. 1.00 Nov. 22, 2007 Page 1242 of 1692
REJ09B0360-0100