SH7764 Datasheet, PDF (334/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
• When the external bus is 64 bits wide:
External Bus SDRAM Address
64 bits
SH7764 Address
128 Mbits Bank (2)
(16 Mbytes) Row (12)
8 M × 16
Column (9)
256 Mbits Bank (2)
(32 Mbytes) Row (12)
8 M × 32
Column (9)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
14 13
12 25 24 23 22 21 20 19 18 17 16 15
11 10 9 8 7 6 5 4 3
14 13
12 25 24 23 22 21 20 19 18 17 16 15
11 10 9 8 7 6 5 4 3
11.4.6 SDRAM Mode Register (SDMR)
This register is used to set the SDRAM mode register.
Since SDMR is not physically contained in the MCU, reading SDMR is invalid. Only the write
addresses have a meaning for the SDRAM, and the write data is ignored.
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMR
Address
1
1
111
1
111
0
100
0
[Support Settings]
(1) BL = 4 (When external bus is 64 bits wide) or
8 (When external bus is 32 bits wide)
(2) BT = Sequential
(3) LMODE(CL) = 2 or 3
(4) OPCODE = Burst read & burst write
When other settings than the above are made, correct
operation is not guaranteed.
SDRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
"L"
CS_N
"L"
RAS_N
"L"
CAS_N
"L"
WE_N
Rev. 1.00 Nov. 22, 2007 Page 278 of 1692
REJ09B0360-0100