SH7764 Datasheet, PDF (825/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.9 Receive Missed-Frame Counter Register (RMFCR)
RMFCR is a 16-bit counter that indicates the number of frames that could not be saved in the
receive buffer and so were discarded during reception. When the receive FIFO overflows, the
receive frames in the FIFO are discarded. The number of frames discarded at this time is counted.
When the value in this register reaches H'FFFF, count-up is halted. The counter value is cleared to
0 by a write to this register with any value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MFC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 16 
Initial
Value
All 0
15 to 0 MFC[15:0] All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
Missed-Frame Counter
These bits indicate the number of frames that are
discarded and not transferred to the receive buffer
during reception.
Rev. 1.00 Nov. 22, 2007 Page 769 of 1692
REJ09B0360-0100