SH7764 Datasheet, PDF (197/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Floating-Point Unit (FPU)
<Big endian>
63
0
Floating-point register
DR (2i)
63
FR (2i)
0
FR (2i+1)
63
Memory area
8n
32 31
0
8n+3 8n+4 8n+7
<Little endian>
63
0
Floating-point register
DR (2i)
*¹, *²
63
0
FR (2i) FR (2i+1)
63
0
DR (2i)
*²
63
0
FR (2i)
FR (2i+1)
63
0
DR (2i)
63
FR (2i)
0
FR (2i+1)
63
Memory area
4n+3
32 31
0 63
4n 4m+3 4m 8n+3
32 31
0 63
32 31
0
8n 8n+7 8n+4 8n+7 8n+4 8n+3 8n
(1) SZ = 0
(2) SZ = 1, PR = 0
(3) SZ = 1, PR = 1
Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used.
2. The bit-location of DR register is used for double precision format when PR = 1.
(In the case of (2), it is used when PR is changed from 0 to 1.)
Figure 6.5 Relation between SZ Bit and Endian
Rev. 1.00 Nov. 22, 2007 Page 141 of 1692
REJ09B0360-0100