SH7764 Datasheet, PDF (1076/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.3.10 LCDC Horizontal Sync Signal Register (LDHSYNR)
LDHSYNR specifies the timing of the generation of the horizontal (scan direction) sync signals
for the LCD module.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
HSYNW[3:0]




HSYNP[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name Initial Value R/W Description
15 to HSYNW 0000
12
[3:0]
R/W Horizontal Sync Signal Width
Set the width of the horizontal sync signals (CL1 and
Hsync) (unit: character = 8 dots).
Specify to the value of (the number of horizontal sync
signal width) -1.
Example: For a horizontal sync signal width of 8 dots.
HSYNW = (8 dots/8 dots/character) -1 = 0 =
H'0
11 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 0 HSYNP
[7:0]
01010000
R/W Horizontal Sync Signal Output Position
Set the output position of the horizontal sync signals
(unit: character = 8 dots).
Specify to the value of (the number of horizontal sync
signal output position) -1.
Example: For a LCD module with a width of 640 pixels.
HSYNP = [(640/8) +1] -1 = 80 = H'50
In this case, the horizontal sync signal is
active from the 648th through the 655th dot.
Note: The following conditions must be satisfied:
HTCN ≥ HSYNP+HSYNW+1
HSYNP ≥ HDCN+1
Rev. 1.00 Nov. 22, 2007 Page 1020 of 1692
REJ09B0360-0100