SH7764 Datasheet, PDF (482/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.7 NMI Flag Control Register (NMIFCR)
NMIFCR is a 32-bit readable and partially writable with conditions register that has an NMI flag
(NMIFL bit) that can be read or cleared by software. The NMIFL bit is automatically set to 1 by
hardware when an NMI interrupt is detected by the INTC. To clear the NMIFL bit, write 0 to the
bit by software.
The NMIFL bit value does not affect NMI acceptance by the CPU. Although the NMI request
detected by the INTC is cleared by CPU acceptance, the NMIFL bit is not cleared automatically.
Even if 0 is written to the NMIFL bit before the NMI request is accepted by the CPU, the NMI
request is not canceled.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIL               NMIFL
Initial value: — 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/(W)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31
NMIL
30 to 17 —
Initial
Value
R/W
Undefined R
All 0
R
Description
NMI Input Level
Indicates the level of the signal input at the NMI pin.
This bit can be read to determine the NMI pin level.
This bit cannot be modified.
0: Low level is input to the NMI pin
1: High level is input to the NMI pin
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 426 of 1692
REJ09B0360-0100