SH7764 Datasheet, PDF (58/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Table 1.1 SH7764 Features
Items
CPU
Specification
• Renesas Technology original SuperH architecture (SH-4A)
• Compatible with SH-1, SH-2, SH-3, and SH-4 at object code level
• 32-bit internal data bus
• General register file:
 Sixteen 32-bit general registers (and eight 32-bit shadow registers)
 Seven 32-bit control registers
 Four 32-bit system registers
 Register bank for high-speed response to interrupts
• RISC-type instruction set (upward compatible with SH series):
 Instruction length: 16-bit fixed-length basic instructions for improved
code efficiency
 Load/store architecture
 Delayed branch instructions
 Conditional execution
 Instruction set based on C language
• Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
• Instruction execution time: Up to two instructions/cycle
• Address space: 4 Gbytes
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• Internal multiplier
• Eight-stage pipeline
• Harvard architecture
Rev. 1.00 Nov. 22, 2007 Page 2 of 1692
REJ09B0360-0100