SH7764 Datasheet, PDF (821/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit
Bit Name
16
RFOFIP
15 to 12 
11
CNDIP
10
DLCIP
9
CDIP
8
TROIP
7
RMAFIP
6, 5

4
RRFIP
3
RTLFIP
Initial
Value
0
All 0
0
0
0
0
0
All 0
0
0
R/W Description
R/W Receive FIFO Overflow Interrupt Enable
0: Overflow interrupt is disabled
1: Overflow interrupt is enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Carrier Not Detect Interrupt Enable
0: Carrier not detect interrupt is disabled
1: Carrier not detect interrupt is enabled
R/W Detect Loss of Carrier Interrupt Enable
0: Detect loss of carrier interrupt is disabled
1: Detect loss of carrier interrupt is enabled
R/W Delayed Collision Detect Interrupt Enable
0: Delayed collision detect interrupt is disabled
1: Delayed collision detect interrupt is enabled
R/W Transmit Retry Over Interrupt Enable
0: Transmit retry over interrupt is disabled
1: Transmit retry over interrupt is enabled
R/W Receive Multicast Address Frame Interrupt Enable
0: Receive multicast address frame interrupt is disabled
1: Receive multicast address frame interrupt is enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Receive Residual-Bit Frame Interrupt Enable
0: Receive residual-bit frame interrupt is disabled
1: Receive residual-bit frame interrupt is enabled
R/W Receive Too-Long Frame Interrupt Enable
0: Receive too-long frame interrupt is disabled
1: Receive too-long frame interrupt is enabled
Rev. 1.00 Nov. 22, 2007 Page 765 of 1692
REJ09B0360-0100