SH7764 Datasheet, PDF (871/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
21.3.2 CPU Bus Wait Setting Register (BUSWAIT)
BUSWAIT is a register that specifies the number of wait cycles to be inserted during an access
from the CPU to this module.
This register can be modified even when the SCKE bit in SYSCFG is 0.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
BWAIT[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15 to 4 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3 to 0 BWAIT[3:0] 1111 R/W CPU Bus Wait
Specifies the number of wait cycles to be inserted
during an access to this module.
0000:
Setting prohibited
0100:
4 wait cycle (6 access cycles)
0110:
6 wait cycle (8 access cycles)
1111:
15 wait cycles (17 access cycles)
(initial value)
Rev. 1.00 Nov. 22, 2007 Page 815 of 1692
REJ09B0360-0100