SH7764 Datasheet, PDF (498/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.15 Interrupt Mask Register 1 (INT2MSKR1)
INT2MSKR1 is a 32-bit readable/writable register that sets masking for each source indicated in
the interrupt source register. Interrupts whose corresponding bits in INT2MSKR1 are set to 1 are
not notified to the CPU.
INT2MSK1 is initialized to H'FFFF FFFF (mask state) by a reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
— SCIF2 —
—
—
—
— VDC2 — USB EtherC
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R R/W R
R
R
R
R R/W R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
— _LCDC —
—
IIC
—
SRC SRC
ODFI IDEI
—
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R R/W R
R R/W R R/W R/W R
Initial
Bit
Bit Name Value R/W Function
Description
31 to 26 —
All 1 R
Reserved
These bits are always read as 1.
The write value should always be
1.
Masks interrupts for
each peripheral
module.
[When writing]
25
SCIF2 1
R/W Masks SCIF2 interrupts
0: Invalid
24 to 20 —
19
VDC2
18
—
All 1 R
Reserved
These bits are always read as 1.
The write value should always be
1.
1: Interrupts are
masked
[When reading]
0: No mask setting
1
R/W Masks VDC2 interrupts
1: Mask setting
1
R
Reserved
This bit is always read as 1. The
write value should always be 1.
17
USB
1
R/W Masks USB interrupts
16
EtherC 1
R/W Masks EtherC interrupts
15 to 8
—
All 1 R
Reserved
This bit is always read as 1. The
write value should always be 1.
7
LCDC 1
R/W Masks LCDC interrupts
Rev. 1.00 Nov. 22, 2007 Page 442 of 1692
REJ09B0360-0100