SH7764 Datasheet, PDF (883/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
21.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)
CFIFO, D0FIFO and D1FIFO are port registers that are used to read data from the FIFO buffer
memory and writing data to the FIFO buffer memory.
There are three FIFO ports: the CFIFO, D0FIFO and D1FIFO ports. Each FIFO port is configured
of a port register (CFIFO, D0FIFO, D1FIFO) that handles reading of data from the FIFO buffer
memory and writing of data to the FIFO buffer memory, a select register (CFIFOSEL,
D0FIFOSEL, D1FIFOSEL) that is used to select the pipe assigned to the FIFO port, and a control
register (CFIFOCTR, D0FIFOCTR, D1FIFOCTR).
Each FIFO port has the following features.
• The DCP FIFO buffer should be accessed through the CFIFO port.
• Accessing the FIFO buffer using DMA transfer should be performed through the D0FIFO or
D1FIFO port.
• The D1FIFO and D0FIFO ports can be accessed also by the CPU.
• When using functions specific to the FIFO port, the pipe number (selected pipe) specified by
the CURPIPE bits cannot be changed (when the DMA transfer function is used, etc.).
• Registers configuring a FIFO port do not affect other FIFO ports.
• The same pipe should not be assigned to two or more FIFO ports.
• There are two FIFO buffer states: the access right is on the CPU side and it is on the SIE side.
When the FIFO buffer access right is on the SIE side, the FIFO buffer cannot be accessed from
the CPU.
• These addresses, H'FE40 0180 of D0FIFO port register and H'FE40 01C0 of D1FIFO port
register shown in table 21.2 are exclusive for 16- or 32- byte consecutive accesses. When
accesses the FIPO buffer with 16- or 32-byte consecutively, the bit width has to be 32bit.
Select to be used either of endian. If D0FIFO or D1FIFO is accessed in cycle steal mode or by
the CPU, address H'FE400018 for D0FIFO or H'FE40001C for D1FIFO should be accessed.
However, in the case of access to CFIFO, D0FIFO or D1FIFO as little-endian data with any
width other than 21 bits, the address is changed. See tables 21.8 to 21.10 for details.
These registers are initialized by a power-on reset.
Rev. 1.00 Nov. 22, 2007 Page 827 of 1692
REJ09B0360-0100