SH7764 Datasheet, PDF (432/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
7
DL
0
R/W DREQ Level and DREQ Edge Select
6
DS
0
R/W Specify the detecting method of the DREQ pin input
and the detecting level.
These bits are valid only in CHCR0 and CHCR1.
In channels 0 and 1, also, if the transfer request source
is specified as an on-chip peripheral module or if an
auto-request is specified, these bits are invalid.
00: DREQ detected at low level (DREQ)
01: DREQ detected at falling edge
10: DREQ detected at high level
11: DREQ detected at rising edge
5
TB
0
R/W Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
Burst mode cannot be used when the on-chip
peripheral module is the transfer request source.
4, 3
TS[1:0] 00
R/W DMA Transfer Size Specify
See the description of TS[2] (bit 20).
2
IE
0
R/W Interrupt Enable
Specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request (DEI)
to the CPU when the TE bit is set to 1. To confirm the
completion of DMA transfer, issue the SYNCO
instruction after the dummy read to unreserved space
when generating an interrupt request to the CPU.
0: Interrupt request is disabled.
1: Interrupt request is enabled.
Rev. 1.00 Nov. 22, 2007 Page 376 of 1692
REJ09B0360-0100