SH7764 Datasheet, PDF (461/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
CLKOUT
Address
T1 T2 Taw T1 T2
CS
RD
Data
WEn
DACKn
(Low-active)
DTENDn
(Low-active)
RDY
Note: DTEND is asserted during the last transfer unit of the DMA transfer.
When the transfer unit is divided into several bus cycles and CS is negated
between bus cycles, DTEND is also divided.
Figure 12.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 1.00 Nov. 22, 2007 Page 405 of 1692
REJ09B0360-0100