SH7764 Datasheet, PDF (612/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
16.2 Input/Output Pins
Table 16.1 lists the pins used in the I²C bus interface.
Table 16.1 Pin Configuration
Pin Name
I/O
Description
SCL
I/O
I²C serial clock input/output pin*
SDA
I/O
I²C serial data input/output pin*
Note: * The SCL and SDA pins are open drain pins (3.3 V).
16.3 Register Descriptions
Table 16.2 shows the IIC register configuration. Table 16.3 shows the register state in each
operating mode.
Table 16.2 Register Configuration
Register Name
Abbreviation R/W
Area P4
Address*¹
Area 7
Address*¹
Access
Size
Slave control register
ICSCR
R/W H'FFE7 0000 H'1FF7 0000 8
Master control register
ICMCR
R/W H'FFE7 0004 H'1FF7 0004 8
Slave status register
Master status register
ICSSR
ICMSR
R/(W)*² H'FFE7 0008 H'1FF7 0008 8
R/(W)*³ H'FFE7 000C H'1FF7 000C 8
Slave interrupt enable
register
ICSIER
R/W H'FFE7 0010 H'1FF7 0010 8
Master interrupt enable
register
ICMIER
R/W H'FFE7 0014 H'1FF7 0014 8
Clock control register
ICCCR
R/W H'FFE7 0018 H'1FF7 0018 8
Slave address register
ICSAR
R/W H'FFE7 001C H'1FF7 001C 8
Master address register ICMAR
R/W H'FFE7 0020 H'1FF7 0020 8
Receive data register
ICRXD
R/W H'FFE7 0024 H'1FF7 0024 8
Transmit data register
ICTXD
R/W H'FFE7 0024 H'1FF7 0024 8
Notes: 1. P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
2. Only 0 can be written to bits 4 to 0 to clear the flags.
3. Only 0 can be written to bits 6 to 0 to clear the flags.
Rev. 1.00 Nov. 22, 2007 Page 556 of 1692
REJ09B0360-0100