SH7764 Datasheet, PDF (844/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
30
TDLE
0
R/W Transmit Descriptor Ring End
When set to 1, this bit indicates that the
corresponding descriptor is the last one of the
descriptor ring.
29
TFP1
0
R/W Transmit Frame Positions 1 and 0
28
TFP0
0
R/W These bits relate the transmit buffer to the transmit
frame. The settings of these bits and the TBL bits
should be logically correct in the consecutive
descriptors.
00: Transmission of the frame of the transmit buffer
specified by this descriptor is continued. (The
frame is incomplete.)
01: The transmit buffer specified by this descriptor
contains the end of the frame (The frame is
complete.)
10: The transmit buffer specified by this descriptor is
the start of the frame (The frame is incomplete.)
11: The contents in the transmit buffer specified by
this descriptor correspond to one frame (single-
frame/single-buffer).
Rev. 1.00 Nov. 22, 2007 Page 788 of 1692
REJ09B0360-0100