SH7764 Datasheet, PDF (896/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
12

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
11 to 0 DTLN[11:0] H'000 R
Receive Data Length
Indicates the length of the receive data.
While the FIFO buffer is being read, these bits
indicate the different values depending on the RCNT
bit value as described below.
• RCNT = 0:
This module sets these bits to indicate the length
of the receive data until the CPU (DMAC) has
read all the received data from a single FIFO
buffer plane.
While BFRE is 1, these bits retain the length of
the receive data until BCLR is set to 1 even after
all the data has been read.
• RCNT = 1:
This module decrements the value indicated by
these bits each time data is read from the FIFO
buffer. (The value is decremented by one when
MBW is 0, and by two when MBW is 1.)
This module sets these bits to 0 when all the data
has been read from one FIFO buffer plane. However,
in double buffer mode, if data has been received in
one FIFO buffer plane before all the data has been
read from the other plane, this module sets these bits
to indicate the length of the receive data in the
former plane when all the data has been read from
the latter plane.
When RCNT is 1, reading these bits while the FIFO
buffer is being read returns the latest value within
150 ns after the FIFO port read cycle.
Notes: 1. Only 0 can be read and 1 can be written to.
2. Only 1 can be written to.
Rev. 1.00 Nov. 22, 2007 Page 840 of 1692
REJ09B0360-0100