SH7764 Datasheet, PDF (1392/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
26.5 Usage Note
26.5.1 Note on Access Register
After the FL bit in SRCCTRL is set to 1, it takes 3 cycles of peripheral bus clock until the FLF bit
in SRCSTAT is set to 1. While the CPU executes the next instruction without waiting the register
write completion. Accordingly, the FLF set status cannot be read by the instruction immediately.
To check the execution status of flash processing, dummy read the SRCCTRL or SRCSTAT after
following the SRCCTRL write instruction and wait until the FLF bit is set.
26.5.2 Note on Flash Processing
After set 1 to the FL bit in SRCCTRL, the SRC continues exchange processing with setting to 0
after following the destination of the data that has already input. Flash processing allowed to be
executed only under the condition that the destination bit of audio data has input completely and
no following data exists.
In a case that implement the exchange processing after the flash processing, clear the internal
work memories with using either way listed as follows.
• Set 1 to the CL bit in SRCCTRL.
• Set 0 to the SRCEN bit in SRCCTRL and back to 1.
Rev. 1.00 Nov. 22, 2007 Page 1336 of 1692
REJ09B0360-0100