SH7764 Datasheet, PDF (1495/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Watchdog Timer and Reset
29.5.2 Power-On Reset by Watchdog Timer Overflow
The transition time from the watchdog timer overflowed to the power-on reset state (watchdog
timer reset setup time) is 9 clock cycle of the EXTAL input clock and thereafter equal to or more
than 18 clock cycles of the peripheral clock (Pck).
The power-on reset time (watchdog timer reset holding time) by the watchdog timer overflowed is
equal to or more than one cycle of input signal from EXTAL pin and thereafter equal to or more
than 5 clock cycles of the peripheral clock (Pck).
Power-On Reset by Watchdog timer Overflowed in Normal Operation
The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is
asynchronous with both the EXTAL pin input clock and the CLKOUT pin output clock because
the STATUS [1:0] pins output timing is synchronous with the peripheral clock (Pck).
EXTAL
input
CLKOUT
output
WDT overflow
signal
STATUS[1:0]
output
LL (normal)
HH (reset)
LL (normal)
WDT reset
setup time
WDT reset
holding time
Figure 29.6 STATUS Output by Watchdog timer overflow Power-On Reset
during Normal Operation
Power-On Reset by Watchdog timer Overflowed in Sleep Mode
The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is
asynchronous with both the EXTAL pin input clock and the CLKOUT pin output clock because
the STATUS [1:0] pins output timing is synchronous with the peripheral clock (Pck).
Rev. 1.00 Nov. 22, 2007 Page 1439 of 1692
REJ09B0360-0100