SH7764 Datasheet, PDF (649/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
Initial
Bit
Bit Name Value R/W Description
4
UDMAEN 0
R/W UDMAEN is Ultra DMA enable. When Ultra DMA is used,
set this bit to 1. Set it to '0' when using the multiword
DMA or PIO mode.
3
DESE 0
R/W DESE controls the descriptor table operation mode.
1. Validating the descriptor function.
0. Invalidating the descriptor function.
2
R/W
0
R/W R/W is FIFO read/write. 1 = FIFO read (data-in operation
at DMA transfer), 0 = FIFO write (data-out operation at
DMA transfer).
Set this bit to 1 when reading data from the ATAPI
device.
Set it to '0' when writing data to the ATAPI device.
1
STOP 0
R/W STOP terminates a DMA transfer.
When writing
0: Ignored
1: Stop a data transfer
When reading
0: The stop command is not issued.
1: The data transfer stop command is issued.
It will become 0 when the next DMA starts.
Note: Transfer cannot be restarted from the address at
which DMA transfer has been stopped.
0
START 0
R/W START initiates a DMA transfer. If this bit set to 1 then
the DMA transfer is started. 0 writing is ignored.
When writing
0: Ignored
1: DMA transfer start
When reading
0: DMA transfer is not active
1: Busy in DMA transfer
Note: Must not access the Task File Register while
DMA is active.
Rev. 1.00 Nov. 22, 2007 Page 593 of 1692
REJ09B0360-0100