SH7764 Datasheet, PDF (411/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
(3) Method of Linear-to-Tiled Memory Address Translation
Table 11.19 shows the specifications for translating linear addresses into the tiled memory
addresses.
Table 11.19 Correspondence between Linear Addresses and Tiled Memory Addresses
MWX
Linear Address
LT- Number of Pixels 27 to
GBM (Number of Tiles) 21 20 19 18 17 16 15 14 13 12 11 10 9
0
512 (16)
↑↑↑↑↑↑↑↑↑8765
1024 (32)
↑↑↑↑↑↑↑↑98765
2048 (64)
↑ ↑ ↑ ↑ ↑ ↑ ↑ 10 9 8 7 6 5
4096 (128)
↑ ↑ ↑ ↑ ↑ ↑ 11 10 9 8 7 6 5
1
512 (16)
↑ ↑ ↑ ↑ ↑ ↑ 15 14 9 8 7 6 5
1024 (32)
↑ ↑ ↑ ↑ ↑ ↑ ↑ 10 9 8 7 6 5
2048 (64)
↑ ↑ ↑ ↑ ↑ ↑ 11 10 9 8 7 6 5
4096 (128)
↑ ↑ ↑ ↑ ↑ 12 11 10 9 8 7 6 5
4 to
87650
12 11 10 9 ↑
13 12 11 10 ↑
14 13 12 11 ↑
15 14 13 12 ↑
13 12 11 10 ↑
14 13 12 11 ↑
15 14 13 12 ↑
16 15 14 13 ↑
The LTGBM bit in the LTCn register specifies the pixel format of the image data in graphics bit
mode. LTGBM = 0 specifies 8 bits/pixel and LTGBM = 1 specifies 16 bits/pixel. MWX in the
table indicates the memory width in terms of the number of pixels.
The memory width can be 512, 1024, 2048, or 4096. Only formats of 8 bits/pixel and 16 bits/pixel
are available for linear-to-tiled memory address translation.
Figure 11.27 shows the operation of linear-to-tiled memory address translation. In the figure,
LTAM represents the linear-to-tiled memory address translation area start address mask registers
and LTAD represents the linear-to-tiled memory address translation area start address registers.
Rev. 1.00 Nov. 22, 2007 Page 355 of 1692
REJ09B0360-0100