SH7764 Datasheet, PDF (747/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
• Configuration Mode
This mode is entered after the module is released from reset. All required settings in the
control register should be defined in this mode, before SSI_CH0 to SSI_CH5 are enabled by
setting the EN bit.
Setting the EN bit causes SSI_CH0 to SSI_CH5 to enter the module enabled mode.
• Module Enabled Mode:
Operation in this mode depends on the selected operating mode. For details, see section 18.4.3
(4), Transmit Operation and section 18.4.3 (5), Receive Operation.
(4) Transmit Operation
Transmission can be controlled in one of two ways: either DMA or an interrupt driven.
DMA driven is preferred to reduce the CPU load. In DMA control mode, an underflow or
overflow of data or DMAC transfer end is notified by using an interrupt.
The alternative is using the interrupts that SSI_CH0 to SSI_CH5 generate to supply data as
required. This mode has a higher interrupt load as SSI_CH0 to SSI_CH5 are only double buffered
and will require data to be written at least every system word period.
When disabling SSI_CH0 to SSI_CH5, the SSI clock* must be supplied continuously until
SSI_CH0 to SSI_CH5 enter in the idle state, indicated by the IIRQ bits in SSISR0 to SSISR5.
Figure 18.19 shows the transmit operation in the DMA controller mode. Figure 18.20 shows the
transmit operation in the Interrupt controller mode.
Note: * SCKD = 0: Clock input through the SSISCK[5:0] pins
SCKD = 1: Clock input through the AUDIO_CLK[5:0] pins
Rev. 1.00 Nov. 22, 2007 Page 691 of 1692
REJ09B0360-0100