SH7764 Datasheet, PDF (463/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
12.5.4 DACK Output Division and External Request
The DMA transfer unit is divided into multiple bus cycles when a longword access is performed
for an external device with 8-bit or 16-bit data bus, or when a word access is performed for an 8-
bit external device.
Note that the DACK output is divided to align the data unit like the CS output when a setting is
made so that a DMA transfer unit is divided into multiple bus cycles and the CS output is negated
between bus cycles.
12.5.5 DMA Transfer to DMAC Prohibited
Do not perform DMA transfer with the DMAC register specified as the transfer source or transfer
destination.
12.5.6 NMI Interrupt
When an NMI interrupt occurs, the DMA transfer is stopped. After returning from the NMI
interrupt routine, set all channels again, and then restart the DMA transfer.
Rev. 1.00 Nov. 22, 2007 Page 407 of 1692
REJ09B0360-0100