SH7764 Datasheet, PDF (78/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Classification Symbol
I/O
ATAPI interface IDED15 to
I/O
(ATAPI)
IDED0,
IDED15_M to
IDED0_M
IDEA2 to IDEA0, O
IDEA2_M to
IDEA0_M
IODACKI,
O
ODACK_M
IODREQ,
I
IODREQ_M
IDECS1,
O
IDECS0,
IDECS1_M,
IDECS0_M
IDEIOWR,
O
IDEIOWR_M
IDEIORD,
O
IDEIORD_M
IDEIORDY,
I
IDEIORDY_M
IDEINT,
I
IDEINT_M
IDERST,
O
IDERST_M
DIRECTION, O
DIRECTION_M
Name
IDE data bus
Function
Bidirectional data bus.
IDED15_M to IDED0_M are mirror
pins.
IDE address bus IDE address output.
IDEA2_M to IDEA0_M are mirror
pins.
IDEDMA
acknowledge
Primary channel DMA acknowledge
signal (active low).
IODACK_M is a mirror pin.
IDEDMA request Primary channel DMA request signal
(active high).
IODREQ_M is a mirror pin.
IDE chip select
Primary channel chip select signal
(active low).
IDECS1_M and IDECS0_M are
mirror pins.
IDE write
Primary channel write signal (active
low).
IDEIOWR_M is a mirror pin.
IDE read
Primary channel read signal (active
low).
IDEIORD_M is a mirror pin.
IDE ready
Primary channel ready signal (active
high).
IDEIORDY_M is a mirror pin.
IDE interrupt
Primary channel interrupt request
signal (active high).
IDEINT_M is a mirror pin.
IDE reset
Primary channel ATAPI device reset
signal (active low).
IDERST_M is a mirror pin.
Direction
External level shifter direction signal
(0 when writing to the device).
DIRECTION_M is a mirror pin.
Rev. 1.00 Nov. 22, 2007 Page 22 of 1692
REJ09B0360-0100