SH7764 Datasheet, PDF (721/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W
31 to 29 
All 0 R
28
DMEN
0
R/W
27
UIEN
0
R/W
26
OIEN
0
R/W
25
IIEN
0
R/W
24
DIEN
0
R/W
23, 22 CHNL[1:0] 00
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Enable
Enables or disables a DMA request.
0: A DMA request is disabled.
1: A DMA request is enabled.
Underflow Interrupt Enable
Enables or disables an underflow interrupt.
0: An underflow interrupt is disabled.
1: An underflow interrupt is enabled.
Overflow Interrupt Enable
Enables or disables an overflow interrupt.
0: An overflow interrupt is disabled.
1: An overflow interrupt is enabled.
Idle Mode Interrupt Enable
Enables or disables an idle mode interrupt.
0: An idle mode interrupt is disabled.
1: An idle mode interrupt is enabled.
Data Interrupt Enable
Enables or disables a data interrupt.
0: A data interrupt is disabled.
1: A data mode interrupt is enabled.
Channel
These bits indicate the number of channels in each
system word.
00: 1 channel per system word
01: 2 channels per system word
10: 3 channels per system word
11: 4 channels per system word
Rev. 1.00 Nov. 22, 2007 Page 665 of 1692
REJ09B0360-0100