SH7764 Datasheet, PDF (48/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Floating-Point Unit (FPU)
Table 6.1 Floating-Point Number Formats and Parameters.................................................. 133
Table 6.2 Floating-Point Ranges .......................................................................................... 134
Table 6.3 Bit Allocation for FPU Exception Handling......................................................... 142
Section 7 Memory Management Unit (MMU)
Table 7.1 Register Configuration.......................................................................................... 158
Table 7.2 Register States in Each Processing State .............................................................. 158
Table 7.3 Cache Size and Countermeasure for Avoiding Synonym Problems..................... 188
Section 8 Caches
Table 8.1 Cache Features...................................................................................................... 207
Table 8.2 Store Queue Features ............................................................................................ 207
Table 8.3 Register Configuration.......................................................................................... 211
Table 8.4 Register States in Each Processing State .............................................................. 211
Section 9 On-Chip Memory
Table 9.1 IL Memory Addresses .......................................................................................... 237
Table 9.2 Register Configuration.......................................................................................... 238
Table 9.3 Register States in Each Processing Mode ............................................................. 238
Table 9.4 Protective Function Exceptions to Access On-Chip Memory .............................. 242
Section 10 Clock Pulse Generator (CPG)
Table 10.1 Pin Configuration and Functions of CPG ............................................................. 248
Table 10.2 Clock Operating Modes ........................................................................................ 249
Table 10.3 Register Configuration.......................................................................................... 250
Table 10.4 Register States in Each Operating Mode .............................................................. 250
Section 11 Memory Controller Unit (MCU)
Table 11.1 MCU Pin Configuration........................................................................................ 258
Table 11.2 External Memory Space Map ............................................................................... 261
Table 11.3 MODE Pin Settings for Memory Bus Width of Area 0 ........................................ 261
Table 11.4 Endian Setting by Pin ........................................................................................... 262
Table 11.5 Register Configuration.......................................................................................... 263
Table 11.6 Address Multiplexing ........................................................................................... 277
Table 11.7 32-Bit External Device/Big-Endian Access and Data Alignment
(Areas 0 and 3)...................................................................................................... 308
Table 11.8 16-Bit External Device/Big-Endian Access and Data Alignment
(Areas 0 and 3)...................................................................................................... 308
Table 11.9 8-Bit External Device/Big-Endian Access and Data Alignment
(Areas 0 and 3)...................................................................................................... 309
Table 11.10 32-Bit External Device/Little-Endian Access and Data Alignment
(Areas 0 and 3).................................................................................................. 310
Rev. 1.00 Nov. 22, 2007 Page xlviii of lvi