SH7764 Datasheet, PDF (1299/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.4 Graphic Image Area Registers (GROPSWH1 to GROPSWH4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16






GROPSH[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






GROPSW[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 26 
Initial
Value
All 0
25 to 16
15 to 10
GROPSH
[9:0]

H'000
All 0
9 to 0
GROPSW H'000
[9:0]
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W These bits specify the height of the graphic image
area in number of lines.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W These bits specify the width of the graphic image
area in number of panel clock cycles.
Rev. 1.00 Nov. 22, 2007 Page 1243 of 1692
REJ09B0360-0100