SH7764 Datasheet, PDF (1318/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
The VDC2 assumes that the external sync signals are input with the horizontal and vertical sync
signal timing for the LCD panel conforming to the VESA standard. This register adjusts the
phases of the external input sync signals when they are sampled in the VDC2.
24.6.17 Sync Signal Size Register (SYNSIZE)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16






SYN_HEIGHT[9:0]
Initial value: 0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





SYN_WIDTH[10:0]
Initial value: 0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 26 
Initial
Value R/W
All 0 R
25 to 16 SYN_HEIGHT H'20D R/W
[9:0]
15 to 11 
All 0 R
10 to 0 SYN_WIDTH H'35A R/W
[10:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits specify the height including the vertical
blanking interval in number of lines.
Initial value: H'20D = 525 lines
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits specify the width including the
horizontal blanking interval in number of panel
clock cycles.
Initial value: H'35A = 858 dots
Rev. 1.00 Nov. 22, 2007 Page 1262 of 1692
REJ09B0360-0100