SH7764 Datasheet, PDF (50/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Timer Unit (TMU)
Table 14.1 Pin Configuration.................................................................................................. 471
Table 14.2 Register Configuration.......................................................................................... 472
Table 14.3 Register States in Each Processing Mode ............................................................. 473
Table 14.4 TMU Interrupt Sources......................................................................................... 486
Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.1 Pin Configuration.................................................................................................. 492
Table 15.2 Register Configuration.......................................................................................... 493
Table 15.3 Register State in Each Operation Mode................................................................ 494
Table 15.4 SCSMR Settings ................................................................................................... 514
Table 15.5 Bit Rates and SCBRR Settings
(Asynchronous Mode, BGDM = 0, ABCS = 0).................................................... 515
Table 15.6 Bit Rates and SCBRR Settings (Clock Synchronous Mode) ................................ 516
Table 15.7 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode) .......................................................................................... 517
Table 15.8 Maximum Bit Rates with External Clock Input (Asynchronous Mode)............... 517
Table 15.9 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode,
t_Scyc = 12t_pcyc)......................................................................................................... 518
Table 15.10 SCSMR Settings and SCIF Communication Formats ...................................... 528
Table 15.11 SCSMR and SCSCR Settings and SCIF Clock Source Selection..................... 529
Table 15.12 Serial Communication Formats (Asynchronous Mode).................................... 531
Table 15.13 SCIF Interrupt Sources ..................................................................................... 549
Section 16 I²C Bus Interface (IIC)
Table 16.1 Pin Configuration.................................................................................................. 556
Table 16.2 Register Configuration.......................................................................................... 556
Table 16.3 Register State in Each Operating Mode................................................................ 557
Table 16.4 Suggested Settings for CDF and SCGD ............................................................... 571
Table 16.5 Description on Symbols of I²C Bus Data Format ................................................. 574
Section 17 ATAPI
Table 17.1 Pin Configuration.................................................................................................. 588
Table 17.2 ATA Task File Register Map................................................................................ 589
Table 17.3 ATAPI Packet Command Task File Register Map ............................................... 590
Table 17.4 ATAPI Interface Control Register Map................................................................ 591
Table 17.5 Data Transfer Modes ............................................................................................ 611
Section 18 Serial Sound Interface (SSI)
Table 18.1 Pin Configuration.................................................................................................. 621
Table 18.2 SSI_DMAC0 Register Configuration ................................................................... 621
Table 18.3 SSI_DMAC0 Register State in Each Operating Mode ......................................... 624
Rev. 1.00 Nov. 22, 2007 Page l of lvi