SH7764 Datasheet, PDF (1304/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Initial
Bit
Bit Name Value R/W Description
31 to 26 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 GROPEDPV H'000 R/W These bits specify the vertical start position of the
[9:0]
α control area in number of lines.
15 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 0 GROPEDPH H'000 R/W These bits specify the horizontal start position of
[9:0]
the α control area in number of panel clock cycles.
Note: Layer 1 is the bottom image which has no α control target, so the above settings are
prohibited for layer 1.
GROPEDPH + 16
Internal HSync
GROPEW
Graphic image area
α control area
Figure 24.11 α Control Area Settings
Rev. 1.00 Nov. 22, 2007 Page 1248 of 1692
REJ09B0360-0100