SH7764 Datasheet, PDF (289/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 Caches
31
24 23
15 141312
Address field _{1 1 1 1 0 1 0 1 * * * * * * * * *}
31
Data field
Way
Longword data
Entry
L : Longword specification bits
* : Don't care
543210
L 00
0
Figure 8.8 Memory-Mapped OC Data Array (Cache size = 32 Kbytes)
8.6.5 Memory-Mapped Cache Associative Write Operation
Associative writing to the IC and OC address arrays may not be supported in future SuperH-
family products. The use of instructions ICBI, OCBI, OCBP, and OCBWB is recommended.
These instructions handle ITLB misses, and notify instruction TLB miss exceptions and data TLB
miss exceptions, thus providing a sure way of controlling the IC and OC. As a transitional
measure, the SH-4A generates address errors when this function is used. If compatibility with
previous products is a crucial consideration, on the other hand, the MMCAW bit in EXPMASK
(H'FF2F 0004) can be set to 1 to enable this function. However, instructions ICBI, OCBI, OCBP,
and OCBWB should be used to guarantee compatibility with future SuperH-family products.
Rev. 1.00 Nov. 22, 2007 Page 233 of 1692
REJ09B0360-0100