SH7764 Datasheet, PDF (720/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit
Bit Name
Initial
Value R/W Description
1
TXFIFOFULM0 1
R/W TXFIFOFUL0 (3) Interrupt Source Mask
(TXFIFOFULM3)
Masks the TXFIFOFUL0 (3) interrupt source.
0: The TXFIFOFUL0 (3) interrupt source is not masked.
1: The TXFIFOFUL0 (3) interrupt source is masked.
0
RXFIFOEMPM0 1
R/W RXFIFOEMP0 (3) Interrupt Source Mask
(RXFIFOEMPM3)
Masks the RXFIFOEMP0 (3) interrupt source.
Note:
0: The RXFIFOEMP0 (3) interrupt source is not
masked.
1: The RXFIFOEMP0 3) interrupt source is masked.
Descriptions within parenthesis "( )" indicate those for SSIDMINTMR1.
18.3.16 Control Registers 0 to 5 (SSICR0 to SSICR5)
SSICR0 to SSICR5 control interrupts, select each polarity status, and set operating mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


 DMEN UIEN OIEN IIEN DIEN CHNL[1:0]
DWL[2:0]
SWL[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL 
CKDV[2:0]
MUEN  TRMD EN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 664 of 1692
REJ09B0360-0100