SH7764 Datasheet, PDF (659/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.9 Termination Flag and Descriptor DMA Start Address
Bit: 31 30
DTEND —
Initial value: — 0
R/W: R/W R
29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
DDSTAA[2:0]
DDSTA[25:16]
0 —————————————
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DDSTA[15:2]
—
—
Initial value: ^{— — — — — — — — — — — — — — 0}
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Initial
Bit
Bit Name Value
31
DTEND Undefined
30 to 29 —
All 0
28 to 26 DDSTAA Undefined
[2:0]
25 to 2 DDSTA Undefined
[25:2]
1, 0
—
All 0
R/W Description
R/W DTEND controls the termination of a descriptor DMA
operation.
1: Terminating the descriptor DMA operation
(When DTEND is 1, the system recognizes that the
descriptor table is the last one.)
0: Validating the descriptor table
(When DTEND is 0, the system reads the DMA transfer
count, transfers the DMA, and reads the next descriptor
table.)
R Reserved
R/W DDSTAA shows the DMA start SDRAM area in
descriptor operation mode.
001: SDRAM area 1
010: SDRAM area 2
Other than above: Setting prohibited.
R/W DDSTA shows the DMA start address in descriptor
operation. Bits 25 to 0 are used to set the descriptor
table start address on a byte basis.
Bits 4 to 2 must be set 0, and bits 1 and 0 are ignored
because it is necessary to secure the boundary of 256-
bit addresses in the DMA start address.
R Reserved
The valid flag and descriptor DMA start address should be set in the descriptor table base address
+ "m" in the memory, where the value of m is any multiple of 2 (such as 0, 2, 4, …).
Rev. 1.00 Nov. 22, 2007 Page 603 of 1692
REJ09B0360-0100