SH7764 Datasheet, PDF (920/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
4
SACK
0
R/W*¹ Setup Transaction Normal Response Interrupt Status
Indicates the status of the setup transaction normal
response interrupt when the host controller function
is selected.
0: SACK interrupts not generated
1: SACK interrupts generated
This module detects the SACK interrupt when ACK
response is returned from the peripheral device
during the setup transactions issued by this module,
and sets this bit to 1. Here, if software has set the
corresponding interrupt enable bit to 1, this module
generates the SACK interrupt.
3 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Notes: 1. To clear the status indicated by the bits in this register, write 0 only to the bits to be
cleared; write 1 to the other bits.
2. A change in the status indicated by the BCHG bit can be detected even while the clock
supply is stopped (while SCKE is 0), and the interrupt is output when the corresponding
interrupt enable bit is enabled. Clearing the status through software should be done
after enabling the clock supply.
No interrupts other than BCHG can be detected while the clock supply is stopped (while
SCKE is 0).
21.3.18 BRDY Interrupt Status Register (BRDYSTS)
BRDYSTS is a register that indicates the BRDY interrupt status for each pipe.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
BRDY BRDY BRDY BRDY BRDY BRDY BRDY BRDY BRDY BRDY
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W*¹ R/W*¹ R/W*¹ R/W*¹ R/W*¹ R/W*¹ R/W*¹ R/W*¹ R/W*¹ R/W*¹
Rev. 1.00 Nov. 22, 2007 Page 864 of 1692
REJ09B0360-0100