SH7764 Datasheet, PDF (35/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Figure 11.1 Block Diagram of MCU............................................................................................. 256
Figure 11.2 Correspondence between Virtual Address Space and External Memory Space......... 260
Figure 11.3 Basic Timing of SRAM Interface .............................................................................. 317
Figure 11.4 Example of 32-Bit Data-Width SRAM Connection................................................... 318
Figure 11.5 Example of 16-Bit Data-Width SRAM Connection................................................... 319
Figure 11.6 Example of 8-Bit Data-Width SRAM Connection..................................................... 319
Figure 11.7 SRAM Interface Wait Timing (Software Wait Only) ................................................ 320
Figure 11.8 SRAM Interface Wait Cycle Timing (Wait Cycle Insertion by RDY Signal) ........... 321
Figure 11.9 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting) .............. 322
Figure 11.10 Connection Example of Synchronous DRAMs for 64-Bit Data Bus (Area 1) ......... 325
Figure 11.11 Connection Example of Synchronous DRAMs for 32-Bit Data Bus (Area 1) ......... 326
Figure 11.12 Basic SDRAM Interface Timing (1) Burst Read...................................................... 328
Figure 11.13 Basic SDRAM Interface Timing (2) Burst Write..................................................... 329
Figure 11.14 Basic SDRAM Interface Timing (3) Single Read .................................................... 330
Figure 11.15 Basic SDRAM Interface Timing (4) Single Write ................................................... 331
Figure 11.16 Basic SDRAM Interface Timing (5) Burst Read Timing
(Bank Open Mode; Same Row Address Accessed) ................................................. 333
Figure 11.17 Basic SDRAM Interface Timing (6) Burst Read Timing
(Bank Open Mode; Different Row Addresses Accessed)........................................ 334
Figure 11.18 Basic SDRAM Interface Timing (7) Burst Write Timing
(Bank Open Mode; Same Row Address Accessed) ................................................. 335
Figure 11.19 Basic SDRAM Interface Timing (8) Burst Write Timing
(Bank Open Mode; Different Row Addresses Accessed)........................................ 336
Figure 11.20 Arbitration of Access Requests (1) .......................................................................... 341
Figure 11.21 Arbitration of Access Requests (2) .......................................................................... 341
Figure 11.22 Block Diagram of MCU
(with Symbols Shown for Multi-Step Arbitration Circuit) ...................................... 345
Figure 11.23 Arbitration Sequence................................................................................................ 348
Figure 11.24 Reflection of Data Written by SuperHyway Bus Device ......................................... 351
Figure 11.25 Data Arrangement in Tiled Memory Areas.............................................................. 353
Figure 11.26 Schematic of Linear-to-Tiled Memory Address Translation.................................... 354
Figure 11.27 Operation of Linear-to-Tiled Memory Address Translation .................................... 356
Section 12 Direct Memory Access Controller (DMAC)
Figure 12.1 Block Diagram of DMAC .......................................................................................... 360
Figure 12.2 Round-Robin Mode.................................................................................................... 389
Figure 12.3 Changes in Channel Priority in Round-Robin Mode.................................................. 390
Figure 12.4 Data Flow of Dual Address Mode.............................................................................. 391
Figure 12.5 Example of DMA Transfer Timing in Dual Address Mode
(Source: Ordinary Memory, Destination: Ordinary Memory) ................................... 392
Rev. 1.00 Nov. 22, 2007 Page xxxv of lvi