SH7764 Datasheet, PDF (1302/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.6 Graphic Image Start Position Registers (GROPDPHV1 to GROPDPHV4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16






GROPDPV[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






GROPDPH[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 26 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 GROPDPV H'000
[9:0]
R/W These bits specify the vertical display start position
of the graphic image area in number of lines.
15 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 0
GROPDPH H'000
[9:0]
R/W These bits specify the horizontal display start
position of the graphic image area in number of
panel clock cycles.
Note: The display start address is offset as follows (see figure 24.9).
Vertical offset: (GROPDPV value) + 1 line
Horizontal offset: (GROPDPH value) + 16 panel clock cycles
24.6.7 α Control Area Registers (GROPEWH2 to GROPEWH4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16






GROPEH[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






GROPEW[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 1246 of 1692
REJ09B0360-0100