SH7764 Datasheet, PDF (962/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
21.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)
PIPEnCTR is a register that is used to confirm the buffer memory status for the corresponding
pipe, change and confirm the data PID sequence bit, determine whether auto response mode is set,
determine whether auto buffer clear mode is set, and set a response PID for PIPE1 to PIPE9. This
register can be set regardless of the pipe selection in PIPESEL.
This register is initialized by a power-on reset. PID[1:0] are initialized by a USB bus reset.
(1) PIPEnCTR (n = 1 to 5)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BSTS INBUFM CSCLR CSSTS —
AT
REPM
ACLRM SQCLR SQSET SQMON PBUSY
—
—
—
PID[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W*² R
R R/W R/W R/W*¹ R/W*¹ R
R
R
R
R R/W R/W
Bit
Bit Name
15
BSTS
Initial
Value R/W
0
R
Description
Buffer Status
Indicates the FIFO buffer status for the pertinent
pipe.
0: Buffer access from CPU is disabled.
1: Buffer access from CPU is enabled.
The meaning of this bit depends on the settings of
the DIR, BFRE, and DCLRM bits as shown in table
21.11.
Rev. 1.00 Nov. 22, 2007 Page 906 of 1692
REJ09B0360-0100