SH7764 Datasheet, PDF (205/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
Section 7 Memory Management Unit (MMU)
The SH-4A supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit
physical address space. Address translation from virtual addresses to physical addresses is enabled
by the memory management unit (MMU) in the SH-4A. The MMU performs high-speed address
translation by caching user-created address translation table information in an address translation
buffer (translation lookaside buffer: TLB).
The SH-4A has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB
copies are stored in the ITLB by hardware. A paging system is used for address translation. It is
possible to set the virtual address space access right and implement memory protection
independently for privileged mode and user mode.
In view of flag functions of the MMU, TLB compatible mode (four paging sizes with four
protection bits) and TLB extended mode (eight paging sizes with six protection bits) are provided.
Selection between TLB compatible mode and TLB extended mode is made by setting the relevant
control register (bit ME in the MMUCR register) by software.
The flag functions of the MMU are explained in parallel for both TLB compatible mode and TLB
extended mode.
Rev. 1.00 Nov. 22, 2007 Page 149 of 1692
REJ09B0360-0100