SH7764 Datasheet, PDF (1240/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
23.3 Register Specifications
The CPU writing to the registers, excluding the system control registers, is prohibited after
rendering has started and until the TRAP command is executed, except for the drawing halted
period specified by the INT command. However, if a CPU write to the interrupt enable register
(IER) conflicts with a WPR command write, the CPU write is given priority. Hereafter, “reset”
refers to both a hardware reset and software reset unless specified otherwise. A hardware reset is a
power-on reset.
Table 23.5 Register Configuration
Class
Register Name Abbrev. RW
System control System control SCLR
R/W
STatus
SR
R
Status register SRCR
W
clear
Interrupt enable IER
R/W
Interrupt
command ID
ICIDR
R
Memory control Return address 0 RTN0R R
Return address 1 RTN1R R
Display list start DLSAR R/W
address
2-dimensional
SSAR
R/W
source area start
address
Rendering start RSAR
R/W
address
Work area start WSAR R/W
address
Source stride
SSTRR R/W
Destination stride DSTRR R/W
Endian conversion ENDCVR R/W
control
Color control Source
STCR
R/W
transparent color
WPR*¹
N
N
N
Y
N
Y
Y
N
Y
Y
Y
Y
Y
N
Y
Area P4
Address*²
H'FFEA 0000
H'FFEA 0004
H'FFEA 0008
H'FFEA 000C
H'FFEA 0010
H'FFEA 0040
H'FFEA 0044
H'FFEA 0048
H'FFEA 004C
H'FFEA 0050
H'FFEA 0054
H'FFEA 0058
H'FFEA 005C
H'FFEA 0060
H'FFEA 0080
Area 7
Address*²
H'1FEA 0000
H'1FEA 0004
H'1FEA 0008
H'1FEA 000C
H'1FEA 0010
H'1FEA 0040
H'1FEA 0044
H'1FEA 0048
H'1FEA 004C
H'1FEA 0050
H'1FEA 0054
H'1FEA 0058
H'1FEA 005C
H'1FEA 0060
H'1FEA 0080
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Rev. 1.00 Nov. 22, 2007 Page 1184 of 1692
REJ09B0360-0100