SH7764 Datasheet, PDF (1329/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.27 T1004 Video Start Position Register (T1004OFFSET)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





T1004OFFSET_H[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 11 
Initial
Value R/W
All 0 R
10 to 0 T1004OFFSET 0
R/W
_H[10:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits adjust the horizontal phase of the video
signal and blanking interval in 2-pixel units.
Specifying a larger value shifts the video display
position left. The lowest two bits (bits 1 and 0)
should always be 0.
Table 24.10 shows an example of register settings to display the video at the top-left corner of the
active area.
Table 24.10 Example of Register Settings for T-1004 Output
Register
Setting
Graphics blocks GROPDPHV1 to H'0026_0072
GROPDPHV4
Display control SYNSIZE
block
H'020D_35A
T1004OFFSET H'0000_0010
Description
Starts video output from line 40 with respect to
the internal Vsync and panel clock cycle 131
with respect to the internal Hsync.
Specifies 525 lines for the vertical sync signal
period and 858 panel clock cycles for the
horizontal sync signal.
Adjusts the horizontal phase of the video
signal and blanking interval.
Increasing the register value by H'4 shifts the
display position left by two pixels; decreasing
the value by H'4 shifts the display position
right by two pixels.
Rev. 1.00 Nov. 22, 2007 Page 1273 of 1692
REJ09B0360-0100